Silicon Carbide (SiC) is a desirable material for high-power and high-temperature semiconductor devices due to its high breakdown field, high thermal conductivity, and wide bandgap. However, to take advantage of the high breakdown field in a high-voltage device, an efficient edge termination is needed. More specifically, field crowding at the edge of the device results in device breakdown at the edge of the device, which in turn decreases the blocking voltage of the device well below the ideal blocking voltage (i.e., the blocking voltage of the ideal parallel-plane device). Thus, edge termination is an important issue in the design of SiC semiconductor devices and particularly for high-power SiC semiconductor devices.
One type of edge termination utilized for SiC semiconductor devices is a Junction Termination Extension (JTE). FIG. 1 illustrates an exemplary SiC semiconductor device, namely, a thyristor 10 that includes a number of JTE wells 12, 14, and 16. The thyristor 10 includes a substrate 18, an injection layer 20, a field stop layer 22, a drift layer 24, a base layer 26, and an anode layer 28. In order to form the JTE wells 12, 14, and 16, the base layer 26 is etched down to the drift layer 24 as illustrated. The JTE wells 12, 14, and 16 are then formed by ion implantation into an exposed surface of the drift layer 24. An anode contact 30 is formed on the anode layer 28, a cathode contact 32 is formed on a bottom surface of the substrate 18 opposite the injection layer 20, and gate contacts 34 and 36 are formed on corresponding gate regions 38 and 40 in the base layer 26. As a result of the etching of the base layer 26 down to the drift layer 24 to form the JTE wells 12, 14, and 16, a corner 42 is formed. The corner 42 causes electric field crowding, which in turn decreases the blocking voltage of the thyristor 10 to less than the ideal blocking voltage.
Thus, there is a need for an edge termination for a SiC semiconductor device that results in a blocking voltage that approaches the ideal blocking voltage for the ideal parallel-plane device.